1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having a relatively thin active region such as a MOS (Metal Oxide Semiconductor) type field effect transistor (referred to as SOI-MOSFET hereinafter) and a method of manufacturing thereof.
2. Description of the Background Art
An SOI-MOSFET to which the present invention is mainly applied will be explained first taking a complementary type MOS (referred to as CMOS hereinafter) as an example of the background technology of the present invention.
A CMOS having low consumption power and superior noise immunity is important in seeking high integration density and high speed operation. A sectional view of a conventional CMOS of not the SOI type but the so-called bulk type is shown in FIG. 1A. Referring to FIG. 1A, a CMOS has an n well region 2 formed in the proximity of the surface of a p type silicon substrate 1. A p channel type MOSFET 4 comprising a polycrystalline silicon gate 4 as the main element is formed on n well region 2. An n channel type MOSFET 6 comprising a polycrystalline silicon gate 5 as the main element is formed at the surface of p type silicon substrate 1 in the region other than n well region 2. A field oxide film 7 insulates and isolates n well region 2 from the other region. When such a bulk type CMOS is reduced in element size, parasitic thyristor is activated by noise from outside so that abnormal current flows from the power supply terminal to the ground terminal to stop the circuit operation (latch up phenomenon). This also induces problems such as soft error by .alpha.-particle.
A sectional view of a CMOS having an SOI type structure is schematically shown in FIG. 1B. Referring to FIG. 1B, this SOI type CMOS has semiconductor layers 9 and 10 such as of silicon layers formed island-like by a field insulating film 7 on a silicon substrate 1 with an insulator layer 8 therebetween. Semiconductor layer 9 has an n type channel region and p type source/drain regions of p channel MOSFET 4 formed including polycrystalline silicon gate 3. Semiconductor layer 10 has a p type channel region and n type source/drain regions of n channel MOSFET 6 formed. Such a CMOS of the SOI structure has each element and also the substrate insulation-separated so that there is no current path leading to soft error and latch up. This is advantageous to reduction of element size. It is also advantageous to high speed operation since interconnection capacitance and junction capacitance are reduced by the lower insulating layer (refer to Ouyou Butsuri (Applied Physics) Vol. 54, No. 12 (1985) pp. 1274-1283, "SOI Technology").
A structure of a conventional SOI-MOSFET and a method of manufacturing thereof will be explained hereinafter with reference to FIGS. 2, and 3A-3F. Referring to FIG. 2, a conventional SOI-MOSFET has an insulator layer 12 formed on a silicon substrate 11. A relatively thin silicon layer 13 of approximately 300-1500 .ANG. is formed on insulator layer 12. Near the center of silicon layer 13, a channel region 14 having a low p type impurity concentration (for example, 10.sup.16 -10.sup.17 /cm.sup.3) is formed. An additional source region 15 and an additional drain region 16 having an n type impurity concentration of the middle degree (for example, 10.sup.18 /cm.sup.3) are formed adjacent to the sides of channel region 14.
Additional source region 15 and additional drain region 16 have a source region 17 and a drain region 18 connected, respectively, each of a high n type impurity concentration (for example 10.sup.19 -10.sup.20 /cm.sup.3).
A gate electrode 20 is formed above channel region 14 with a dielectric thin film 19 therebetween. A sidewall spacer 21 is formed at the sidewalls of gate electrode 20. Silicon layer 13, gate electrode 20 and sidewall spacer 21 are covered with an interlayer insulating film 22. A contact hole 23 is provided in interlayer insulating film 22. An interconnection layer 24 is connected to gate electrode 20, source region 17 and drain region 18 through each contact hole 23.
When positive voltage is applied to gate electrode 20 in the SOI-MOSFET of the above structure, carriers (electrons) of the n conductivity type are induced towards the upper layer of p type channel region 14, whereby that upper layer is inverted to an n conductivity type identical to the conductivity of source region 17 and drain region 18, or additional source region 15 and additional drain region 16. This allows current to flow between source region 17 and drain region 18. Because the concentration of the n type carriers induced at the upper layer of channel region 14 varies depending on the gate voltage, the current amount flowing across channel region 14 can be controlled by the gate voltage. This explains the operation of a MOSFET.
Additional drain region 16 has the so-called LDD (Lightly-Doped Drain) structure, serving to reduce the electric field in the proximity of the boundary between drain region 18 and gate electrode 20 to suppress generation of electron-hole pairs caused by impact ionization phenomenon. A thin film SOI-MOSFET having a relatively thin silicon layer 13 of, for example, 500-1500 .ANG. thickness, has the following characteristics in comparison with a conventional SOI-MOSFET having a relatively thick silicon layer of approximately 5000 .ANG.. Since channel region 14 where current flows is very thin, the application of a gate voltage causes channel region 14 to become entirely depleted. This allows the depletion layer of channel region 14 to be controlled reliably by gate electrode 20 independent of the effect of the drain voltage. This reduces the effect of electric field from drain region 18 to channel region 14. As a result, the V.sub.D -I.sub.D characteristic degradation of FIG. 4A seen in conventional bulk type MOSFETs excluding the SOI type where current increases suddenly by a high drain voltage, i.e. the punch through phenomenon, is suppressed. It will therefore be possible to operate stably a transistor having a short gate length.
A method of manufacturing a conventional SOI-MOSFET having the structure of FIG. 2 will be explained hereinafter with reference to FIGS. 3A-3F. First, oxygen ions are implanted into a silicon substrate 11 at an injection energy of 200 KeV and a dosage of 2.times.10.sup.18 /cm.sup.3. Then, the substrate is subjected to heat treatment of approximately 1350.degree. C. An insulating layer 12 is formed in silicon substrate 11 leaving a thin silicon layer 13 on the surface. Next, silicon layer 13 is processed in an island-like manner to form an active region (FIG. 3A). Impurities of p type are injected into silicon layer 13 to form a channel region 14. Next, a dielectric thin film 19 is formed by thermal oxidation of the surface of silicon layer 13. Then, a gate electrode 20 such as of polycrystalline silicon is formed. Ion implantation is carried out using gate electrode 20 as a mask. By implanting phosphorus which is an impurity of n type for example, additional source region 15 and additional drain region 16 are formed (FIG. 3B).
By depositing a CVD insulating film 21a (FIG. 3C) and then carrying out reactive ion etching, a sidewall spacer 21 is formed at the sidewall of gate electrode 20. Some over-etching is necessary in providing sidewall spacer 21. This is to take into consideration unevenness in the thickness of CVD oxide film 21a which is deposited to approximately 3000 .ANG. to leave only sidewall spacer 21 while removing the remainder by etching. This over-etching is responsible for some removal of silicon layer 13 to generate a step as shown in FIG. 3D by arrow A. Specifically, when the application of reactive ion etching to CVD oxide film 21a of, for example, approximately 3000 .ANG. in average is carried out with over-etching of approximately 20% on account of variation in thickness and etching characteristic of CVD oxide film 21a. That is to say, 3000 .ANG. of CVD oxide film 21a is first etched, followed by etching of a time period where 600 .ANG. of CVD oxide film 21a is over-etched. Silicon layer 13 will be over-etched if the thickness of the CVD insulating film deposited thereabove is exactly 3000 .ANG.. A silicon oxide film is generally used for a CVD insulating film, where the selectivity of reactive ion etching to silicon is approximately 5:1. This means that silicon of approximately 120 .ANG. is etched during the time period where over-etching of 600 .ANG. is carried out for a silicon oxide film.
Following the formation of sidewall spacer 21, arsenic ions of 10.sup.19 -10.sup.20 /cm.sup.3 are injected using sidewall spacer 21 as a mask to form source region 17 and drain region 18 of high concentration, as shown in FIG. 3D. Then, an interlayer insulating film 22 is deposited by CVD, followed by formation of a contact hole 23 in a predetermined position in interlayer insulating layer 22. Some over-etching occurs in forming contact hole 23 to result in a depression indicated by arrow B in FIG. 3E. The formation of an interconnection layer 24 completes the manufacture of a thin film SOI-MOSFET of FIG. 3F.
Because a conventional SOI-MOSFET is manufactured having a structure as described above, over-etching occurs in forming sidewall spacer 21 and contact hole 23, resulting in a silicon layer 13 having a thin portion as shown in arrow A of FIG. 3D and arrow B of FIG. 3E. The resistance of this portion is increased to deteriorate the transistor characteristic. The value of drain current I.sub.D with respect to a predetermined drain voltage V.sub.D is decreased as shown in FIG. 4B. There was also a problem that the transistor does not operate due to the fact that there is some portion where silicon layer 13 is completely removed to cut off source region 17 or drain region 18.